Place and Route Application Engineer (1590) San Diego, California

Company:  Mentor Graphics

Job Title:  Place and Route Application Engineer

Job Location: US - CA - San Diego

Job Category:  Applications Engineering / Sales

 

Mentor Graphics Corporation (MENT) is a global technology leader in Electronic Design Automation, providing software and hardware design solutions that help engineers around the world create new and innovative products. Each year, our customers use our tools to push the boundaries of technology in order to deliver smaller, faster and more reliable products that run the world’s high tech devices.

 

Position Overview Learn, use, and support state of the art Mentor Graphics’ Olympus-SoC Place and Route ( PnR a.k.a Physical Design) tools.  Daily activities focus on using the tools at advanced nodes such as 28nm, 20nm, and 16nm, exchanging ideas with other application engineers, helping users find solutions to their physical design challenges, and debugging issues with the tools, customer designs, and flow scripts.  Olympus SoC is being quietly used for PnR by a number of large fabless semiconductor companies for the very largest and most challenging designs at the most advanced process nodes.

The Place & Route Applications Engineer will be responsible for:

•Supporting sales activity with product demonstrations, evaluations, competitive benchmarking, and identifying alignment between customer needs and Mentor Graphics products.

•Providing technical support to customers including technical problem resolution and training.

•Communicating customers’ technical requirements to product marketing.

•Assisting customers with their software evaluations and benchmarks.

 

Job Qualifications The successful candidate will possess the following combination of education and experience:

•BSEE required, MSEE preferred.

•5+ years of EDA or IC design experience in Physical Design or Place and Route, including hands-on experience with one/more of the following tools: Mentor ( Olympus-SoC), Synopsys ( IC Compiler, Physical Compiler), Cadence ( SoC Encounter), and Magma ( Talus, BlastFusion)

•A strong understanding of Netlist-to-GDS flow.  Experience in the areas of Floor planning, placement, CTS, routing. signal integrity, static timing analysis and optimization, thorough understanding and full involvement in implementation of these phases in the physical design flow for large digital ASIC or COT flow SoC ( System-on-Chip) designs.

•Skill with a scripting language such as tcl, perl, or javaScript is preferred.

•Preference for 3+ years of demonstrated success within a software sales environment and a proven track record of promoting and supporting sales growth and new business development.

•Must have a clear understanding of competitive products, excellent communication skills and have a high motivation to learn leading edge technologies. •

Must be creative, persistent, and possess problem solving skills that avoid project stalls.

 

Mentor Benefits Mentor Graphics believes in fostering a work environment that promotes a healthy work-life balance.  Our world class benefits package includes up to 32 days of vacation/holidays per year, 401k matching, Stock purchase plan, annual performance reviews/bonuses, education reimbursement, partially paid Medical/Dental/Vision insurance and much more.

To apply, please click here